Song Zhitang is the Director of State Key Laboratory, Professor of Chinese Academy of Sciences, National Ten Thousands talent, Chief Scientist of National Super 973. He received PhD in Engineering from Xi'an Jiaotong University in 1997.11, and worked as a post doctor in Shanghai Institute of Microsystems, Chinese Academy of Sciences in 1999.11. In 2001.1, he worked as a senior visiting scholar in the Department of Applied Physics, Hong Kong Polytechnic University. In 2002, he collaborated with the Department of Applied Physics, Hong Kong Polytechnic University as a professor. He is currently a special researcher, doctoral supervisor, director of Shanghai Key Laboratory of Memory Nanofabrication Technology, and director of State Key Laboratory of Information Functional Materials, Shanghai Institute of Microsystems and Information Technology. He is chief scientist of national Super 973, National Important Projects and National Integrated Circuit Major Special Projects. He received Leading Talent of Shanghai, Special Allowances of the State Council, Ten Thousands of People's Plan, and National Personnel of Millions of Talents in the 21st Century. He is the pioneer of domestic research on materials and devices of PCRAM and has built a 12-inch PCM special platform (160 million RMB) with Gb-level development capability. He developed the first PCM chip in China, and embedded chips with 15 million sales volume which was first applied in the world. He established the phase change material octahedral configuration theory, applied TiSbTe materials and dual trench isolation diodes in chips. As the country's chief scientist, he undertook four 973 and three 02 national major projects, published 511 papers in Sciences, Nature comm and other journals which is most in the world, 4517 citations; 284 domestic authorized invention patents which is most in China. "Electronic Silica Nano Polishing New Materials and Key Technologies for Industrial Preparation" won the first prize of Shanghai Technology Invention Award.Abstract:
Phase change random access memory (PCRAM) has been successfully applied in the computer storage architecture, as storage class memory, to bridge the performance gap between DRAM and Flash-based solid-state drive due to its good scalability, 3D-integration ability, fast operation speed and compatible with CMOS technology. Focusing on phase change materials and PCRAM for decades, we have successfully developed 128Mb embedded PCRAM chips, which can meet the requirements of most embedded systems. 3D Xpoint (3D PCRAM), invented by Intel and Micron, has been regarded as “a new breakthrough in the last 25 years since the application of NAND in 1989”, which represents the state-of-art memory technology. This technology has some remarkable features, such as the confined device structure with 20 nm size, the metal crossbar electrodes to reduce the resistance variations in PCRAM arrays, and the Ovonic threshold switching selector that can provide a high drive current and a low leakage current. A good understanding of phase change mechanism is of great help to design new phase change materials with fast operation speed, low power consumption and long-lifetime. In this paper, we firstly review the development of PCRAM and different understandings on phase change mechanisms in recent years, and then propose a new view on the mechanism, which is based on the octahedral structure motifs and vacancies. Octahedral structure motifs are generally found in both amorphous and crystalline phase change materials. They are considered to be the based units during phase transition, which are severely defective in the amorphous phase. These configurations turn into more ordered ones after minor local rearrangements, the growth of which result in the crystallization of rocksalt (RS) phase with a large amount of vacancies in the cation sites.
Dr. Lieve Teugels joined imec in Belgium in 2009 as R&D engineer in the Electrodeposition, CMP and Thinning group of the Unit Process and Module division. She received a M.S. in Chemistry from the University of Leuven, Belgium and a PhD in Chemistry from the University of Chicago, Illinois,USA. She works mainly on process development of W, Cu-barrier and III-V CMP as well as fundamental CMP research on the polishing of new materials (e.g. Ru, Mo, Ni).
Chih Chen received the 2016 National Innovation Award, 2017 Outstanding Technology Transfer Award on Electroplating and Application of High (111)-oriented Nanotwinned Cu, 2018 Outstanding Researcher Award, Ministry of Science & Technology, Taiwan. TMS 2018 Application to Practice Award, The Minerals, Metals & Materials Society, USA. His current research interests are reliabilities of microbumps for 3D IC, fabrication and applications of nanotwinned Cu, and low-temperature Cu-to-Cu direct bonding.
David Mezerette is Application Manager, Strategic Accounts, at NOVA Measuring Instruments, Inc. He brings more than eight years of expertise in the development and deployment of optical metrology solutions both for Logic and Memory customers.
Previously, as lead researcher at FOI, he directed the engineering efforts to develop new plasma sources for 300mm plasma etcher and asher. Dr. Mezerette carried out his early research at the Department of Electrical Engineering of the University of Nagoya (Japan), working on plasma characterization and thin film deposition. He holds a PhD in Materials Science and Engineering of the National Polytechnic Institute of Lorraine (France). He has published numerous papers, patents and books.
Tae-Gon KIM is an assistant professor in Department of Smart Convergence Engineering in Hanyang University ERICA. He received his Bachelor, Master and PhD from Metallurgy and Material Science and Engineering in 2001, 2003 and 2008 in Hanyang University ERICA, South Korea, respectively. He studied on semiconductor cleaning and CMP processes supervised by Prof. Jin-Goo Park. He was a postdoctoral research fellow in imec and KU Leuven, Belgium in from 2008 to 2010. He was a senior researcher in a scientific advisor of in-line metrology from 2010 to 2019. In his research career, he has been leading activity on advanced film characterization as well as in-line metrology technique for advanced technology node and in-line 3D-AFM technology for 3-dimensional structure characterization such as sidewall characterization of FinFET and Nanowire. He gave several invited talk for SEMICON Korea, ECS so on.Abstract:
In advanced interconnect, CMP processes are becoming important and proper metrology solutions need to be introduced in order to fulfill the requirement of interconnect technology and their CMP processes. Automated in-line AFM with a sliding stage was demonstrated to show the capabilities of narrow trench measurement in large-scale profiling. Decoupled XY scanner and a sliding stage hybrid AFM system provides good measurement capabilities in dishing and erosion of narrow trench with wide range of scan distance. Therefore, in-line AFM with sliding stage could provide a non-destructive and direct metrology solution for CMP process developments of advanced interconnect.
Wei-Hsin Tien is currently an assistant professor in the department of mechanical engineering at National Taiwan University of Science and Technology since 2014. He received his PhD in Aeronautics and astronautics at University of Washington. He earned Bachelor and Master Degrees in Mechanical Engineering and Power Mechanical Engineering from National Taiwan University and National Tsing Hua University both in Taiwan, respectively. He was a visiting scholar at Universität der Bundeswehr München, Germany and a post-doctor at University of Washington. His main research interests are quantitative flow visualization techniques to measure velocity /temperature/pressure in the fluid flow and microscale flow phenomenon in acoustofluidics and microfluidics.Abstract:
CMP (Chemical-Mechanical Polishing) is one of the key part of the modern semiconductor manufacturing process. In spite of its wide usage as the main planarization technique demanded by advanced lithography and multilevel metallization, much of the physics behind CMP is not completely understood. One of the interesting complexity comes from the slurry flow and the concentration distribution in between the rotating wafer and pad. Due to the complex phenomena at the wafer–pad interface during the CMP process, experimental methods are more appropriate because the development of computational fluid dynamics (CFD) modeling requires more experimental data for validation or even as the input to study the hydrodynamics of slurry flow. Flow visualization (FV) techniques have been applied for this purpose in the past decade. Using color or fluorescent dye, the slurry motion on the pad or even the flow at the wafer–pad interface can be visualized, if the wafer is replaced by a transparent material. Quantitative data, e.g., slurry concentration, can be calculated if more advanced technique such as laser induced fluorescence (LIF) is used. In this presentation, a review of the published works will be given and the unique challenges in visualizing CMP slurry flow will be discussed. Promising new techniques, such as temperature sensitive paint and three-dimensional velocimetry techniques will also be introduced.
Dr. Charles Lin is the Director of technology development for Cu, CMP and Wet Processes at Intel NSG (Non-Volatile Solution Group). His semiconductor industry career started as thin film, CMP, wet clean and etch process and TD engineer and manager in Winbond Electronics since 1991. After serves IC FABs for twelve years, he was appointed as director of product management and technology for FSI (acquired by TEL) provides wet clean and etch product solution to Asian IC FABs. Later, he serves as global Sr. manager of CMP slurry, Cu plating, wet clean and etch materials R&D and product implementation for BASF. In 2010 he focus on integrated process technology, serves a director for new business development across and beyond CMP, wet clean and etch processes for Hermes-Epitek (a business partner of TEL, Ebara, HMI etc.). Prior serves TD director for Intel, he spent four years with Dow chemical was the director of Asia Technology Center for CMP materials develop and implementation to IC FABs.
Charles holds MS, Ph.D. in Materials Eng. and MBA in Management of Technology all from National Chiao-Tung University in Taiwan. He is the first inventor of 37 granted patents globally with nearly 50 journal and international conference papers, as committee of CMPUG-TW and conference chair, received multiple international conference invited talk and hundreds hours of thin film, CMP, wet clean and etch technology lectures for IC FABs, SIA (Taiwan) and universities.Abstract:
The traditional computing memory hierarchy served by SRAM-DRAM-HDD has been decades old, can’t fulfill high speed computing system needs. Intel introduces revolutionary memory hierarchy by combine non-volatile memories of Optane TM + 3D NAND SSD that brings ultra-high speed and density with low energy and small form factor advantages was proven close the traditional DRAM-HDD memory hierarchy performance gap with demonstrated significantly boost system performance from high-end data center down to personal computer.
Since 2015 high cost 2D NVM chip capacity saturated by scaling limitation, 3D NAND chip capacity has been increase over 10X just in 3 years pulled by high data capacity, high speed, low power and light weight end user needs. In coming decade, there will be several order of total memory capacity demand, until 3D NVM exceed 50% monthly global Si wafer start. The high growth potential of 3D NVM memory data density also brings speed, size and energy consumption advantages all enabled by device and process technology advancement. Multiple generation 3D NVM technical path are clearly identified through advanced device and process development that enables more cell stacking to increase chip capacity and reduce memory cost ($/GB).
However, increase cell stacking also increase device topology that leaves high aspect ratio pattern process challenges across film deposition, photolithography, CMP, dry and wet etch processes. Hundreds of memory cell stacking also induce hundreds micron of wafer bending due to memory cell extrinsic material stress build-up which bending is extremely complicated challenge to device and process not only within wafer but even within a die dimension control down to nanometer precision.
3D NAND cell stacking increases wafer topology and bending are perfectly challenging CMP topology reduction and global wafer planarization capability. Knowing CMP is a chemical accelerated -mechanical wearing among wafer-slurry-pad-disk through real-time smarter polisher recipe control within and across the polishing process. Just within the single CMP process, 3D NAND ultra high topology and wafer bending are in real-time dynamic evolve which is essential challenge to control the device precision down to nanometer regime. Among those existing CMP slurry-pad-disk-polisher solutions, no single CMP solution can solely serves coming increasing 3D NAND CMP process challenges and needs. To embrace far over 10X growing demand in the coming decade, cross disciplinary suppliers close collaboration is essential to overcome the unique 3D NAND CMP process. Intel NSG TD is welcome the join efforts from potential qualified CMP suppliers to accelerate the CMP solution readiness ahead of the challenge and demand.
Dr. Hitoshi Morinaga received the B.S. degree in industrial chemistry from Tokyo University of Science in 1986, and Ph.D. in electronics from Tohoku University, Japan, in 1995. In 1986-2004, he worked for Mitsubishi Chemical Corporation, Japan, where he was engaged in development of CMP slurries for memory hard disc, cleaning solutions for semiconductor fabrication (including post Cu-CMP cleaner and RCA replacements). In 2005-2006, he was an Associate Professor of Tohoku University, where he was engaged in R&D and systematization of semiconductor wet process technology (including CMP, cleaning, etching and plating) with Prof. Ohmi. In 2006, he joined FUJIMI Incorporated and has been engaged in development of CMP technologies applied for various applications including semiconductor devices, LED, FPD and industrial design. Dr. Morinaga is presently responsible for new business division at FUJIMI Incorporated, Chairman of FUJIMI Shenzhen Technology, and an executive committee member of Planarization and CMP Society, Japan.Abstract:
To expand into new applications of CMP technologies, it is necessary to develop polishing technologies for a diverse range of materials and shapes. Recent advances in CMP technologies applied to various materials, 3D shapes, and using novel mechanisms that are helping to realize these challenges will be discussed.
Dr. Gerfried Zwicker has studied physics at the Technical University Berlin where he graduated on electroluminescence of II-VI semiconductors for his diploma in physics. At Fritz-Haber-Institute of the Max-Planck-Society, also in Berlin, he investigated surface properties of ZnO crystals for his dissertation. He joined the Fraunhofer Institute for Microstructure Technology IMT in 1985, where he worked on CMOS Technology by using x-ray lithography with an emphasis on reactive ion etching RIE. After his move to North Germany to the Fraunhofer Institute for Silicon Technology ISIT in Itzehoe in 1995 he concentrated on Chemical Mechanical Polishing CMP and was responsible for CMP tool development, consumables evaluation and process adoption for MEMS and powerMOS applications.
Dr. Gerfried Zwicker is founder and organizer of the European CMP Users Meeting since
around 20 years and was co-founder and member of the Executive Committee of the
International Conference on Planarization/CMP Technology ICPT until 2018.
He is author/co-author of more than 50 scientific and technical publications and
book contributions and is co-inventor of 3 patents on semiconductor technology.
After his retirement end of 2018 he offers his longtime experience in
microelectronics as an independent consultant.
More-than-Moore, which covers developments in microelectronics additional to digital functionalities (More Moore) like sensors, actuators, powerMOS, Analog, RF, etc., demands more and more for new planarization technologies. This talk will present examples of CMP processes needed for MEMS and powerMOS devices and will discuss process specifications, consumables and tool requirements and the differentiations to the seemingly advanced CMP processes for memory and logic. The use of More-than-Moore devices is increasing constantly from automotive to mobile phone to IoT applications and will further increase in the future for e.g. autonomous driving. Therefore, many new applications and opportunities for planarization technologies have to be expected.
Chemical Mechanical Planarization User Group
National Taiwan University of Science and Technology
Taiwan Tech Global Research and Industry Alliance (GLORIA)
Taiwan Society for Abrasive Technology (TSAT)
Department of Materials Science and Engineering, NCTU
Metal Industries Research & Development Centre