S.V. Babu, a Distinguished University Professor in the Department of Chemical and Biomolecular Engineering in Clarkson University and director of CAMP during 1999-2016, received his PhD from SUNY at Stony Brook and completed Graduate Study in Chemical Engineering at John Hopkins University. He earned Bachelor and Master Degrees in Chemical Engineering from Andhra University and Indian Institute of Technology both in India, respectively. He was a visiting scientist at the Niels Bohr Institute in Copenhagen, International center for theoretical physics, Trieste, and a post-doctoral scientist at NYU. Prior to joining Clarkson, he was a professor at IIT, Kanpur, during 1972-80
Babu has received numerous awards, including the Lifetime Research Achievement Award from Clarkson University in 2018, Lifetime Achievement Award in Planarization at the 2017 ICPT conf. in Leuven, and the 2017 Intel Outstanding Researcher Award for his research in the field of Chemical Mechanical Planarization. He was also honored for his 20 years of CMP research at Clarkson by the Intel Portland Technology Development CMP staff at the North America CMP User’s Group meeting in Portland, OR, also in 2017. Earlier, he received two faculty development awards from IBM. He was honored in 2010 with the Visiting Professorship for Senior International Scientists by the Chinese Academy of Sciences, Shanghai. In addition, the World Education Congress held in Mumbai honored him in 2012 with an Education Leadership Award for his outstanding leadership and contributions to the field of education.
Babu is a co-author of 31 patents, has supervised 46 Ph.D. and 38 MS students and is a co-author of more than 270 professional publications, including over 200 peer-reviewed publications.
He co-organized many symposia and served as a keynote speaker numerous times.
CMP, in spite of its many shortcomings, has seen unprecedented growth over the last twenty years or so and has become a critical and integral part of the manufacturing sequence of both logic and memory devices. At present, only CMP can meet the stringent planarization requirements demanded by advanced lithography and multilevel metallization. Indeed, in current technologies, both both front and back end processing rely on it and each wafer undergoes a planarization operation over twenty times, a number that is growing. The exposure of the heterogeneous surface of the wafer to billions of particles and reactive chemical reagents which must all be completely removed from the wafer surface even as the feature dimensions continue to decrease creates many challenges that must be mitigated. Even in the face these difficulties, it has been possible to enhance manufacturing yields over shorter and shorter manufacturing time scales for each new generation of devices, reflecting the innovation and creativity of an innumerable number of talented personnel that work in and outside the fab. In this talk, several of these good and not so good ("good, bad and ugly") characteristics of the CMP process technology will be described, focusing on consumables, defects, and post-CMP cleaning.
Dr. Liangchi Zhang is Scientia Professor, Professor of Mechanical Engineering,
Head of the
Laboratory for Precision and Nano Processing Technologies and Director of Research
Training at the
University of New South Wales, Australia. He is also the Fellow of the Australian
Technological Science and Engineering (FTSE). Prior to joining the University of
Sydney in 1992, he
has worked at the University of Cambridge, UK and the National Mechanical
Japan. In 2009, he was invited to take up the prestigious Scientia Professorship at
the University of
New South Wales. Liangchi carries out research on both the fundamentals and
He has published 7 monographs, 15 edited books, 20 book chapters and 450 journal
papers. His book,
“Plastic Bending: Theory and Applications”, has been in multiple languages, with its
republished in 2017.
Silicon, silicon carbide, sapphire and diamond wafers are important materials to advanced manufacturing, because these materials have superior properties such as their mechanical, electrical, electronic, thermal and optical characteristics. However, due to their hardness, brittleness and ease of microstructural changes, their polishing is often associated with surface integrity problems. This presentation will discuss the fundamentals and some practical polishing processes in relation to the material removal mechanics and the similarity and difference of deformation mechanisms when dealing with these materials.
Dr. Manabu Tsujimura received Dr. Degree of engineering from TMU in 2002. He
Corporation in 1974 and has worked in water turbine generating division for 10
years, then moved to
the Precision Machinery Group in 1986 and has worked such as R&D of semiconductor
equipment. He was the president of Precision Machinery Company from 2011 to 2015,
CTO of Ebara
Corporation from 2009 to 2018 and now Fellow of Ebara Corporation. He is Fellow of
JSME, chair to
SEAJ, vice chair of JVIA, visiting professor of Clarkson University, Hanyang
University, SKKU, NTUST,
Since the invention of transistors in 1947, semiconductors have developed in accordance with Moore’s law as proposed in 1965, thanks to successful device development following Dennard’s theory on scaling. Dr. Moore himself recognizes that CMP is essential to interconnect scaling and multi-layering of semiconductors. CMP technology, starting with the development of polishers for bare silicon in the 1980s, has experienced the introduction and growth stages, and is now entering the revolution stage without proceeding to the decline stage. To keep up with the development of semiconductors, which has taken different paths since 2005, high-end CMP for the “More Moore (MM)” devices was developed; then CMP for the “More than Moore (MtM)” devices has taken different paths to handle “high volume / low product mix at low cost” and to handle “low volume / high product mix at low cost,” and should develop even further into a planarization process required for the “Beyond CMOS (BC)” devices anticipated in 2030. CMP, with “Ahead CMP” and “Beyond CMP” as catchwords, will continue to evolve. This paper discusses how CMP technology has developed and continues to develop in accordance with the MM, MtM and BC roadmaps.
JongHeun Lim is CMP Project Leader (PL) of Samsung Electronics. He has 20-year experience in the CMP area. He joined semiconductor R&D center of Samsung Electronics, Hwasung, Korea in 2004. His career is focused on developing the next generation process, materials and equipment of CMP for Memory devices. He was an invited talker for ECS2010, CAMP2011, CAMP2012, CAMP2016 and ICPT2019. He has published more than 30 papers in technical journals and conferences and holds over 50 patents. He received the B.S. and M.S. degrees in chemical engineering from the Seoul National University, Seoul, Korea, in 1998 and 2000, respectively.
Semiconductors have been developed so that transistors can be smaller as generations go by increasing density of devices, improving performance, and operating in low power environments. In this presentation, I will take a look at the challenges and direction of development for next generation chemical mechanical planarization (CMP), focusing on CMP Process, Equipment and Materials. With the shrinkage of semiconductor devices, CMP technology has developed with new breakthroughs. For success of the next generation CMP, we need to find additional solutions for Scratch, Particle, Uniformity, Selectivity and Planarization.
Chemical Mechanical Planarization User Group
National Taiwan University of Science and Technology
Taiwan Tech Global Research and Industry Alliance (GLORIA)
Taiwan Society for Abrasive Technology (TSAT)
Department of Materials Science and Engineering, NCTU
Metal Industries Research & Development Centre